Simulation Pipelined RISC-V CPU
Computer Architecture
 
Description:
  • Implemented a complete simulation of a 8-bit pipelined CPU that runs on the LC-2K instruction architecture. The C program combines the assembler, linker, pipeline, and cache to simulate the LC-2K CPU.
  • The assembler takes as input an LC2K assembly file and outputs its correct machine code representation into a machine code file.
  • The linker that combines multiple machine code files into one, resolving any dependencies between the files.
  • The pipeline is a cycle-accurate behavioral simulator program written in C, complete with data forwarding and simple branch prediction.
  • The CPU cache is used by the processor simulation when the processor accesses addresses. The cache supports a variety of cache configurations:

    • Write Policy
    • Associativity
    • Size
    • Block Size
    • Replacement Policy
Skills:
C, memory management, computer architecture design, operating system design
Statistics:

100%

Autograder Tests
Passed

4

Key
Components

95%

Percentile Rank
Among Classmates

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